Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JPS5348440
Kind Code:
A
Abstract:
PURPOSE: A resistor is inserted into the emitter side of the transistor of the 2nd and 3rd amplifiers which constitute a double-balanced-type differnetial amplifieir, thereby realizing a multiplier circuit which has a small signal-to-noise ratio and suits for an integrated circuit.
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Inventors:
IENAKA MASANORI
Application Number:
JP12278876A
Publication Date:
May 01, 1978
Filing Date:
October 15, 1976
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03G3/10; G06G7/16; G06G7/163; (IPC1-7): G06G7/16; H03G3/10