Title:
MULTIPLIER OR D/A CONVERTER USING CHARGE TRANSFER ELEMENT
Document Type and Number:
Japanese Patent JP2599679
Kind Code:
B2
Abstract:
PURPOSE: To realize analog multiplication with high accuracy by a simpler circuit through the operation of multiplying directly a digital signal by a charge signal sent by the charge transfer element by making up of a separator dividing a charge signal on the charge transfer element into at least two parts having a specific ratio, an output circuit group and a digital signal line.
CONSTITUTION: A 1/2 division separator is processed through the utilization of time division multiplexing. A charge signal injected to a left end of the separator is diffused once on the entire separator and the charge is divided into two region parts having an equal amount of charge signals by a barrier generated by a potential VG impressed to a separator electrode G. The right end region is coupled with independent summing nodes via two paths R+, R- and the charge is accumulated in either of summing nodes based on either of transfer instruction of D1 and D2 after the division operation and the transfer instructions D1, D2 are controlled by the MSB of digital data being a multiplier.
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Inventors:
Yasuo Nagazumi
Application Number:
JP4326293A
Publication Date:
April 09, 1997
Filing Date:
February 08, 1993
Export Citation:
Assignee:
GDS Inc.
Yasuo Nagazumi
Yasuo Nagazumi
International Classes:
G06F7/52; G06F7/523; G06F7/53; G06G7/16; H01L21/339; H01L29/762; H03M1/66; H03M1/74; (IPC1-7): G06G7/16; H01L21/339; H01L29/762; H03M1/66; H03M1/74
Domestic Patent References:
| JP53129945A | ||||
| JP54152850A | ||||
| JP159621B2 | ||||
| JP5637640B2 |
Attorney, Agent or Firm:
Nobuyuki Iida