Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP2551386
Kind Code:
B2
Abstract:
PURPOSE: To provide a four-quadrant multiplier operated at a low voltage and having a wide input voltage range with excellent linearity.
CONSTITUTION: The multiplier consists of a 1st CMOS triple tail cell in which a 1st MOS transistor(TR) pair (M1, M2) inputting a 1st signal Vx in a differential way and a MOS TR M3 driven by a constant current IA and inputting one of 2nd complementary signals Vy are driven by a common constant current source I0 and up of a 2nd CMOS triple tail cell in which a 2nd MOS transistor(TR) pair (M4, M5) receiving a 1st signal Vx in a differential way, a MOS TR M6 driven by a constant current IA and inputting the other of 2nd complementary signals Vy are driven by a common constant current source I0. Then a differential output pair is formed by connecting output pairs of the two CMOS triple tail cells whose polarity differs from each other.
Inventors:
KIMURA KATSUHARU
Application Number:
JP19284594A
Publication Date:
November 06, 1996
Filing Date:
July 25, 1994
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06G7/163; H03C1/00; (IPC1-7): G06G7/163; H03C1/00
Attorney, Agent or Firm:
Hachiman Yoshihiro