Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP3022339
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a quarter square multiplier formed on a semiconductor integrated circuit and operated with low current consumption and a low voltage operation as a simple circuit.
SOLUTION: Outputs of a 1st differential pair Q1, Q2, a 2nd differential pair Q3, Q4, a 3rd differential pair Q5, Q6, and a 4th differential pair Q7, Q8 are connected in parallel. Then a voltage of (1st input signal voltage (Vx)+a 2nd input signal voltage (Vy)+a DC voltage (Vk)) and a null voltage are applied to the TRs Q1, Q2, voltages Vk and (VxfVy) are applied to the TRs Q3, Q4, voltages Vy and (Vy+Vk) are applied to the TRs Q5, Q6, and voltages Vx and (Vy+Vk) are applied to the TRs Q7, Q8 respectively via a resistance sum circuit.
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Inventors:
Katsuji Kimura
Application Number:
JP25776396A
Publication Date:
March 21, 2000
Filing Date:
September 06, 1996
Export Citation:
Assignee:
NEC
International Classes:
H03D7/14; G06G7/164; (IPC1-7): G06G7/163; H03D7/14
Domestic Patent References:
| JP883314A | ||||
| JP8153146A | ||||
| JP7160795A | ||||
| JP8153147A |
Attorney, Agent or Firm:
Asamichi Kato