Title:
MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JP3106584
Kind Code:
B2
Abstract:
PURPOSE: To attain low voltage operation and to increase maximum output amplitude and voltage gain by connecting respective common emitters of the 1st and 2nd differential amplifier circuits to the 1st and 2nd constant current sources.
CONSTITUTION: The constant current sources I11, I12 are inserted between the common emitters of two differential amplifier circuits and the negative pole of a power supply Vcc. Namely transistors(TRs) Q11, Q12 are pnp type pair TRs having the same characteristics and constitute a differential amplifier circuit and both the emitters of the TRs Q11, Q12 are connected to the constant current source I11 (current value I1). On the other hand, TRs Q13, Q14. are npn type pair TRs having the same characteristics and constitute a differential amplifier circuit and both the emitters of the TRs Q13, Q14 are connected to the constant current source I12 (current value I2). Similarly the emitters of TRs Q15, Q16 are connected to a constant current source I13 (current value I3). The constant current sources I11 to I13 are set up so as to supply mutually the same current.
More Like This:
| JP2023173393 | PRODUCT SUM CIRCUIT AND NEURAL NETWORK INCLUDING PRODUCT SUM CIRCUIT |
| JP4103507 | Multiplier and level detector circuit |
| JPH06205057 | MODULATOR |
Inventors:
Hiroshi Inose
Application Number:
JP22883891A
Publication Date:
November 06, 2000
Filing Date:
August 14, 1991
Export Citation:
Assignee:
NEC
International Classes:
G06G7/16; H03D1/18; (IPC1-7): G06G7/16; H03D1/18
Domestic Patent References:
| JP426208A | ||||
| JP372704A | ||||
| JP4156612A | ||||
| JP60146371A | ||||
| JP63308687A | ||||
| JP6324377A |
Attorney, Agent or Firm:
Masanori Fujimaki