Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPH04148266
Kind Code:
A
Abstract:

PURPOSE: To simplify the reset method of a device connected from a CPU on a common bus by prohibiting to newly give the right of using of the common bus to transmit a reset output instruction to a bus arbitrating means, and outputting a reset signal on the common bus immediately when a bus using permission signal becomes meaningless.

CONSTITUTION: Two requests that are the request prohibiting to give the right of bus using newly and an output request of a system reset signal (f) are made to be the output request of one system reset signal (f), and the arbitration of the new right of bus using is stopped only by the output request of this system reset signal (f). Together with it, a bus using permission signal (c) indicating the using condition of a common bus 1 is applied to the output condition of the system reset signal (f), and when the system reset signal (f) is requested to output, as well as the bus using permission signal (c) becomes meaningless, the system reset signal (f) is outputted immediately. Thus, the reset method of devices 3, 4 and 6 connected to the common bus 1 becomes simple.


Inventors:
KIJIMA ATSUSHI
Application Number:
JP27018090A
Publication Date:
May 21, 1992
Filing Date:
October 08, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F15/16; G06F13/362; G06F15/177; (IPC1-7): G06F13/362; G06F15/16
Domestic Patent References:
JPH023812A1990-01-09
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)