Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS6457366
Kind Code:
A
Abstract:
PURPOSE:To attain rapid synchronizing communication between processors by arranging a vector register group to be referred from plural processors, identifying a processor allowed to access, storing a vector data value, and displaying the state of corresponding vector element data. CONSTITUTION:The shared vector register group 100 is connected to plural (four) processors through interface parts 110-113 to store information from the processors in the interface parts 110-113, read out the contents of common vector register bodies 120-0-120-15 constituting the group 100 and the interface parts 110-113 and allow the bodies 120-0-120-15 to correspond to the interface parts 110-113 by a switch matrix 130. Fields for identifying the processors allowed to generate reference requests and a field for storing a vector data value consisting of plural vector element data are formed in each of the bodies 120-0-120-15 to control the status display and reference condition of the data.
Inventors:
INAGAMI YASUHIRO
TAMAOKI YOSHIKO
KITAI KATSUYOSHI
TAMAOKI YOSHIKO
KITAI KATSUYOSHI
Application Number:
JP21275587A
Publication Date:
March 03, 1989
Filing Date:
August 28, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F9/30; G06F9/315; G06F9/52; G06F15/16; G06F15/163; G06F15/167; G06F15/177; G06F15/78; G06F15/80; G06F17/16; (IPC1-7): G06F15/16; G06F15/347
Attorney, Agent or Firm:
Katsuo Ogawa