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Title:
MUTING DEVICE
Document Type and Number:
Japanese Patent JPS59103408
Kind Code:
A
Abstract:

PURPOSE: To avoid time delay by turning on a transistor (TR) switch circuit by the potential difference between a power supply voltage and an output of an integration circuit and turning on a muting TR with the output at the on/off of the power supply voltage.

CONSTITUTION: The integration circuit comprising a resistor 4, a diode 5, and a capacitor 6 is provided between a power supply input terminal 1 and ground and a base is onnected to a connecting point between the resistor 4 and the diode 5 via a resistor 7. The device is formed by the TR8 whose emitter is connected to the power input terminal and the TR9 whose emitter is connected between the diode 5 and the capacitor 6 of the integration circuit, whose collector is connected to the collector of the TR8. Then, the muting is applied without time delay and the time constant at the power supply on/off is decided by one integration circuit.


Inventors:
FUJII KATSUYOSHI
Application Number:
JP21291882A
Publication Date:
June 14, 1984
Filing Date:
December 03, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03F1/00; (IPC1-7): H03F1/00
Domestic Patent References:
JPS4968641A1974-07-03
JPS5796505U1982-06-14
JPS5837212U1983-03-10
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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