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Title:
NOISE REDUCTION CIRCUIT
Document Type and Number:
Japanese Patent JPH0744996
Kind Code:
A
Abstract:

PURPOSE: To provide a noise reduction circuit capable of perfectly removing noise at the time of non-signal without a sound signal, or sufficiently reducing it.

CONSTITUTION: A regenerative signal of a head 2 is supplied to an equalizer amplifier 3, and the output of the amplifier 3 is supplied to a fixed terminal of (a) side of a switch 5 directly, and further, is supplied to the fixed terminal of (b) side of the switch 5 through a resistor 6, and further, is supplied to the movable terminal side of the switch 5 through an FET 16. When the sound signal exists as the output of the amplifier 3, the FET 16 is turned on, and when no sound signal exists, the FET 16 is turned off. When the switch 5 is connected to the (b) side, when no sound signal exists as the output of the amplifier 3, the output of the amplifier 3 is supplied to the movable terminal side of the switch 5 through the resistor 6, and the noise at the time of nonsignal is reduced sufficiently. When the switch 5 is connected to a (c) side, when no sound signal exists as the output of the amplifier 3, a signal path is interrupted, and no output of the amplifier 3 is supplied to the movable terminal of the switch 5, and the noise at the time of non-signal is removed perfectly.


Inventors:
KUBOTANI SHIGEJI
IKEDA RYUZO
Application Number:
JP19039693A
Publication Date:
February 14, 1995
Filing Date:
July 30, 1993
Export Citation:
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Assignee:
AIWA CO
International Classes:
G11B20/02; G11B20/24; H04B1/10; (IPC1-7): G11B20/02; G11B20/24; H04B1/10
Attorney, Agent or Firm:
Kunio Yamaguchi (1 person outside)



 
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