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Title:
DELAY TYPE SEMICONDUCTOR RELAY
Document Type and Number:
Japanese Patent JPH0677798
Kind Code:
A
Abstract:

PURPOSE: To set the delay time to an optimum value in accordance with the classification and the use condition of a load.

CONSTITUTION: A light emitting element 1 and a photoelectric element 2 face opposite to each other. An auxiliary switch element 4 consisting of a depletion MOSFET which has the gate and the drain connected is provided between both ends of the photoelectric element 2. A variable resistance VR1 is connected between the gate and the source of the auxiliary switch element 4. A variable resistance VR2 is connected in series between the drain and the source of the auxiliary switch element 4, and this series circuit is connected between the gate and the source of a main switch element 3 consisting of a MOSFET. Since variable resistances VR1 and VR2 are inserted to the charging route and the discharging route of the capacity component of the main switch element 3, the rising period of time the falling period of time of the main switch element 3 can be controlled in accordance with the load.


Inventors:
MIYAMOTO YASUNORI
Application Number:
JP22664092A
Publication Date:
March 18, 1994
Filing Date:
August 26, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H03K17/08; H03K17/28; H03K17/78; (IPC1-7): H03K17/28; H03K17/08; H03K17/78
Attorney, Agent or Firm:
Ishida Chochichi (2 outside)



 
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