Title:
【発明の名称】可変コミット点を有する先入れ先出しメモリ
Document Type and Number:
Japanese Patent JP3091216
Kind Code:
B2
Abstract:
A first-in, first-out (FIFO) memory configuration comprising a fully addressable memory (e.g. random access memory), a write pointer, a read pointer, and a third, "commit" pointer serving as a boundary between first and second subsets of data stored within the FIFO. During data reception, a comparator circuit compares a predetermined subset of incoming data with a predefined reference data set for determining whether the incoming data should be stored or aborted. This determination establishes the appropriate memory address value for positioning the commit pointer. The first subset of data behind the commit pointer may selectively be stored, while the second subset of data ahead of the commit pointer may selectively be aborted. During data transmission, a status register monitors the readiness of the data medium onto which the data is to be transmitted. If and/or when the data medium is ready to accept data, the commit pointer may be selectively positioned to demarcate data committed for transmission.
Inventors:
James Earl Hamstra
Application Number:
JP33096890A
Publication Date:
September 25, 2000
Filing Date:
November 30, 1990
Export Citation:
Assignee:
National Semiconductor Corporation
International Classes:
G06F5/10; G06F13/12; G11C7/00; H04L13/08; (IPC1-7): G11C7/00; G06F5/06; H04L13/08
Domestic Patent References:
| JP642136A | ||||
| JP59501435A |
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)