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Title:
MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPH056333
Kind Code:
A
Abstract:

PURPOSE: To cover the sum of loads of a bus to be used for I/O processing and a bus to be used for data communication between processors by the total capacity of the buses loaded on a multi-processor system capable of efficiently using the buses for I/O processing and inter-processor data communication processing.

CONSTITUTION: The multi-processor system is provided with common buses 14 connecting between respective processors 10 and I/O devices 15, bus controllers 13 connected between respective processors and the common buses 14 to execute transfer control to the devices 15 and message transmission/ reception control based upon inter-processor communication, I/O processing parts 11 for applying an I/O instruction to each corresponding bus controller 13 at the time of receiving an I/O request, and message communication processing parts 12 for applying an inter-processor communication instruction to each corresponding controller 13 at the time of receiving an inter-processor communication request and constituted the bus to be used for I/O processing and the bus to be used for inter-processor communication can be shared.


Inventors:
NAKAMURA TAKASHI
Application Number:
JP15822991A
Publication Date:
January 14, 1993
Filing Date:
June 28, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/36; G06F15/16; G06F15/177; (IPC1-7): G06F13/36; G06F15/16
Attorney, Agent or Firm:
Yoshiyoshi Ogasawara (2 outside)



 
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