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Title:
DUPLEX OPERATION SYSTEM FOR COMMUNICATION PROTOCOL PROCESSOR
Document Type and Number:
Japanese Patent JPH0637865
Kind Code:
A
Abstract:

PURPOSE: To process a data link with distribution of load by inputting the same frames to both systems at the input side of a protocol processor for the enable and disable states of only the transmission and reception and sending the multiplexed frames at the output side.

CONSTITUTION: The same information are inputted to the receiving circuits of the protocol processing parts 22 of the systems '0' and '1' of a protocol processors 2 respectively. The transmission enable/disable states are written into the control tables of both parts 22 for each link so that the system '0' revolts against the system '1'. Therefore the frame having the link address permitted in the system '0' is received and processed in the system '0' and disused in the system '1'. Meanwhile the frames having different addresses and received from the parts 22 are multiplexed by a frame multiplexed part 23 and sent to a subscriber line terminating circuit. In such a constitution, all data links can be processed with distribution of load and therefore the load of a host control processor is reduced.


Inventors:
SUDA HIDEKAZU
Application Number:
JP19179892A
Publication Date:
February 10, 1994
Filing Date:
July 20, 1992
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F13/00; H04L69/40; H04M3/22; H04Q3/545; H04Q11/04; (IPC1-7): H04L29/14; G06F13/00; H04L29/10; H04M3/22; H04Q3/545; H04Q11/04
Attorney, Agent or Firm:
Akita Aki