Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3028779
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten testing time by unnecessitating the initialization of a cache memory at the time of operation test by means of an LSI tester, thereby accelerating the accessing speed to a main memory.
SOLUTION: A control circuit 6 usually performs access to a cache memory 4 at a high cache memory accessing speed and to a main memory 12 at a main memory accessing speed. At the time of testing an LSI, on the other hand, a tester is replaced with a main memory and, when an address to be accessed is in a cache area, a control circuit 6 performs access to the tester (main memory) at the cache memory accessing speed by sending a control signal to be sent to the cache memory 4 to an BIU 7 (bus interface unit) 7 and performing access to the tester. Therefore, the testing time of the tester can be shortened.
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Inventors:
Ichiro Yoshida
Application Number:
JP33667596A
Publication Date:
April 04, 2000
Filing Date:
December 17, 1996
Export Citation:
Assignee:
NEC
International Classes:
G06F12/16; G06F11/22; G06F12/08; (IPC1-7): G06F11/22; G06F12/08; G06F12/16
Domestic Patent References:
| JP378038A | ||||
| JP5134892A | ||||
| JP232436A |
Attorney, Agent or Firm:
Hiroo Suzuki