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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0613879
Kind Code:
A
Abstract:

PURPOSE: To prevent the noise from a GND line due to the discharging operation of the output load capacitance of an output buffer circuit generated when an output buffer is inverted from H to L from exerting adverse influence on the stable operation of an integrated circuit.

CONSTITUTION: This circuit is constituted of a P type transistor 1 whose source is connected to a power source and whose drain is connected to an output terminal 7, an N type transistor 2 whose drain is connected to the drain of the P type transistor 1 and whose source is connected to the GND and an input terminal 5 connected to the both gate terminals of the P type transistor 1 and the N type transistor 2. Further, at least one output buffer circuit with a feature that a capacitor 3 is connected between the output of an inverter circuit 6 to which the input is connected to the input terminal 5 and the output terminal of the output buffer circuit 6 is mounted.


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Inventors:
YONAMINE TAKASHI
Application Number:
JP16978192A
Publication Date:
January 21, 1994
Filing Date:
June 29, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K17/16; H03K17/687; H03K19/003; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/16; H03K17/687; H03K19/003
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)