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Patent Searching and Data


Title:
LEAD FRAME FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0621319
Kind Code:
A
Abstract:

PURPOSE: To prevent interference among lead wires and to improve characteristics by reducing parasitic capacitance because parasitic capacitance generating among lead wires has been a main factor for deterioration of the characteristics of a semiconductor device to be used in the high frequency region.

CONSTITUTION: An inner lead wire 4 which is unified with the same material as a mount island 3 is provided between an outward lead wire 1 and an outward lead wire 2. An earth bonding pad 11 on a semiconductor element 6 and the inner lead 4 are connected by a bonding wire 12. As a result, parasitic capacitance between the outward lead wire 1 and the outward lead wire 2 is separated by the earth inner lead wire 4, and parasitic capacitance is reduced.


Inventors:
SHOJI AKIHIKO
Application Number:
JP17223492A
Publication Date:
January 28, 1994
Filing Date:
June 30, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/50; (IPC1-7): H01L23/50
Domestic Patent References:
JPS5634346B21981-08-10
JP2072561B
JPH03259560A1991-11-19
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)