PURPOSE: To prevent interference among lead wires and to improve characteristics by reducing parasitic capacitance because parasitic capacitance generating among lead wires has been a main factor for deterioration of the characteristics of a semiconductor device to be used in the high frequency region.
CONSTITUTION: An inner lead wire 4 which is unified with the same material as a mount island 3 is provided between an outward lead wire 1 and an outward lead wire 2. An earth bonding pad 11 on a semiconductor element 6 and the inner lead 4 are connected by a bonding wire 12. As a result, parasitic capacitance between the outward lead wire 1 and the outward lead wire 2 is separated by the earth inner lead wire 4, and parasitic capacitance is reduced.
JPWO2005116300 | Exterior palladium-plated structure of semiconductor parts and manufacturing method of semiconductor devices |
JPS62181454 | ELECTRONIC PART |
JPH11243173 | SEMICONDUCTOR DEVICE |
JPS5634346B2 | 1981-08-10 | |||
JP2072561B | ||||
JPH03259560A | 1991-11-19 |