Title:
INTEGRATED CLOCK-SIGNAL GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JPH0685666
Kind Code:
A
Abstract:
PURPOSE: To obtain a phase locked loop circuit that supplies a system clock with minimum power consumption in response to a frequency being an oscillator input by selecting automatically any of a plurality of oscillators that oscillate different frequencies. CONSTITUTION: An oscillator, generator and amplifier 40 supplies dynamically a 32 kHz system signal by giving a selection signal to a multiplexer 62 depending on an EXTAL signal whose frequency is 4 MHz or 32 kHz. The selection signal allows the multiplexer 62 to select a buffer frequency or a division frequency. When the frequency of the EXTAL signal is equal to a system frequency, a reference clock signal with the buffer frequency is supplied to the multiplexer 62 and when the frequency of the EXTAL signal is 4 MHz, the frequency is divided. That is, a clock control circuit 58 and a frequency edge detector 60 discriminate the frequency of the EXTAL signal to supply the selection signal to an amplifier 50 so that the amplifier 50 has a correct gain. In the case of reducing a lock time with the 32 kHz signal, a system reset signal is used to assert a gain enable signal thereby allowing the amplifier 50 to amplify the EXTAL signal.
Inventors:
MAIKERU II GURADEN
UIRIAMU PII RABAIORETSUTO
UIRIAMU PII RABAIORETSUTO
Application Number:
JP5124893A
Publication Date:
March 25, 1994
Filing Date:
February 18, 1993
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
G06F15/78; H03L7/10; H03L7/14; H03L7/18; G06F1/06; H03L7/183; H03L7/089; (IPC1-7): H03L7/18; G06F1/06; G06F15/78; H03L7/10
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)
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