Title:
【発明の名称】半導体メモリ
Document Type and Number:
Japanese Patent JP3068352
Kind Code:
B2
Abstract:
A semiconductor memory device, wherein memory cell arrays MA11, 12, 13, . . . are arranged in a matrix. First driving circuits Da11, 12, 13, . . . and second driving circuits Db11, 12, 13, . . . are arranged alternately at the intersections of the word driver WD11, 12, 13, . . . columns and the sensing circuit SC11, 12, 13 . . . rows. The first driving circuits Da11, 12, 13, . . . serve to drive the sense amplifiers SA11, 12, 13, . . . of the sensing circuits SC11, 12, 13, . . . , and the second driving circuits Db11, 12, 13, . . . to drive the precharge circuits PC11, 12, 13, . . . and transfer circuits TG11, 12, 13, . . . so that a sensing circuit SC11, 12, 13, . . . is driven by the first and second driving circuits Da11, 12, 13, . . . and Db11, 12, 13, . . . on opposite sides of it.
Inventors:
Masamori Fujita
Application Number:
JP32174592A
Publication Date:
July 24, 2000
Filing Date:
December 01, 1992
Export Citation:
Assignee:
NEC
International Classes:
G11C11/407; G11C5/02; G11C11/401; G11C11/409; G11C11/4091; G11C11/4094; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/409
Domestic Patent References:
| JP63209093A | ||||
| JP6423491A |
Attorney, Agent or Firm:
Naoki Kyomoto