Title:
【発明の名称】ラッチ回路
Document Type and Number:
Japanese Patent JP2541883
Kind Code:
B2
Abstract:
PURPOSE:To reduce the number of control lines. CONSTITUTION:A clock and strobe generating circuit 3 is provided which generates a shift-in clock S9 for data to a shift register 1 and a strobe S7 for data transfer from the shift register 1 to a register 2 based on a clock and data. That is, the operation of the shift-in clock S9 is started when data is in the low level at the time the rise of clock and is in the high level at the time the fall of clock and it is stopped and the strobe S7 for data transfer is outputted when data is in the high level at the time the rise of clock and is in the low level at the time the fall of clock. Thus, it is unnecessary to provide a strobe line.
Inventors:
MATSURA MORIAKI
Application Number:
JP17458991A
Publication Date:
October 09, 1996
Filing Date:
June 19, 1991
Export Citation:
Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
H03K3/037; H03M9/00; (IPC1-7): H03K3/037; H03M9/00
Domestic Patent References:
| JP1228017A |
Attorney, Agent or Firm:
Yoichiro Shimoda (1 person outside)