Title:
【発明の名称】多層配線形成法
Document Type and Number:
Japanese Patent JP2518435
Kind Code:
B2
Abstract:
A process of fabricating a multi-level wiring structure starts with preparation of a semiconductor substrate covered with a lower insulating film, and comprises the steps of forming lower-level wiring strips on the lower insulating film, covering the lower-level wiring strips and exposed portions of the lower insulating film with a first intermediate insulating film, coating the entire surface with an organic glass film, removing the organic film except for pieces of the organic glass film in valleys between the lower-level wiring strips, coating the entire surface with an inorganic glass film, removing the inorganic glass film except for pieces of the inorganic glass film on the pieces of the organic glass film, covering the entire surface with a second intermediate insulating film, and forming upper-level wiring strips on the intermediate insulating film, wherein the pieces of the inorganic glass film prevent the upper-level wiring strips from corrosion due to water vapor produced from the pieces of the organic glass film.
Inventors:
MATSUMOTO YASUHIKO
Application Number:
JP1844790A
Publication Date:
July 24, 1996
Filing Date:
January 29, 1990
Export Citation:
Assignee:
YAMAHA CORP
International Classes:
E21B43/22; H01L21/312; H01L21/3205; H01L21/768; H01L23/532; (IPC1-7): H01L21/3205; H01L21/768
Domestic Patent References:
| JPS63226946A | ||||
| JPH01321658A | ||||
| JPH01185947A | ||||
| JP64045148A | ||||
| JPH02177347A | ||||
| JPS60240138A | ||||
| JPS605527A |
Attorney, Agent or Firm:
Toshiaki Izawa