PURPOSE: To provide a control circuit for an inverter in which the control accuracy of the inverter is enhanced and power consumption is reduced while preventing the switch elements on the upper and lower arms of the inverter from being turned ON simultaneously to produce short circuit current.

CONSTITUTION: A combination of a CPU 51, a D/A converter 52, a triangular wave generator 53, and a comparator 54 generates the essential switching signal, i.e., a PWM signal (output signal c), for each switching element 42. The CPU 51 generates a signal (f) having a logical level being inverted with the switching timing (0°, 180°, 360°) of a sine wave (output signal a). A rise delay circuit 13 generates a signal (output signal g) by delaying the rise of the signal (f) by a delay time (td). On the other hand, a rise delay circuit 13 generates a signal (output signal h) by delaying the rise of the inverted signal (f) (output signal from an inverter circuit 12) by the delay time (td).