Title:
DATA OUTPUT DRIVER WITH PULL-UP DEVICE
Document Type and Number:
Japanese Patent JP3026738
Kind Code:
B2
Abstract:
PURPOSE: To limit a voltage difference between a source node and a gate node to a desired level by providing source and gate nodes to apply voltages and a control means for regulating the voltages to be applied to these nodes.
CONSTITUTION: Another element consisting of the voltage driver of a pull-up NMOS transistor(Tr) QN1 is provided with an inverter INV1, PMOSTrs QP2, QP3 and QP4 and NMOSTrs QN5 and QN6. A node 24 is electrically connected with the input of an inverter INV3. The PMOSTrs QP2 and QP3 mutually operate and functionally form a diode 35. Then, this diode maintains the minimum voltage of a node 32 equal to a power supply voltage VDD, when the Tr QP2 is turned on. Further, the Tr QP3 is turned off because of the configuration of this diode 35, and the node 32 reaches a voltage higher than the voltage VDD because of the operation of a voltage-boosting part 23. As a result, the voltage difference between the gate and source of Tr QN1 is limited, and the service life of an off-chip driver 20 is prolonged.
Inventors:
Sun H Don
Kirihata Toshiaki
Matthew Robert Wardman
Kirihata Toshiaki
Matthew Robert Wardman
Application Number:
JP7024095A
Publication Date:
March 27, 2000
Filing Date:
March 28, 1995
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
H03K17/687; G05F3/24; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/687
Other References:
【文献】米国特許5128563(US,A)
【文献】米国特許5270588(US,A)
【文献】米国特許5065049(US,A)
【文献】米国特許4914323(US,A)
【文献】米国特許4772812(US,A)
【文献】米国特許5300832(US,A)
【文献】欧州特許出願公開130273(EP,A2)
【文献】欧州特許出願公開154370(EP,A1)
【文献】米国特許5270588(US,A)
【文献】米国特許5065049(US,A)
【文献】米国特許4914323(US,A)
【文献】米国特許4772812(US,A)
【文献】米国特許5300832(US,A)
【文献】欧州特許出願公開130273(EP,A2)
【文献】欧州特許出願公開154370(EP,A1)
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)