PURPOSE: To make interlace display possible with improved resolution without raising a cost.

CONSTITUTION: A control circuit 5 supplies the shift clock VCK of 2-fold frequency of horizontal synchronizing signals to a vertical driver 4 and drives the vertical driver 4 continuously in two lines during one horizontal period by the shift clock VCK. When the display of a first field is completed, the video signals of the first field for 240 lines are written in the vertical 480 lines of a liquid crystal display panel 1 two by two lines per each line. The control circuit 5 supplies the timing of a start pulse VSP supplied to the vertical driver 4 at the time of displaying the video signals of a second field for one clock of shift clock earier than the time of displaying the first field.