NAND TYPE NON-VOLATILE MEMORY - 富士通株式会社

Title:

NAND TYPE NON-VOLATILE MEMORY

Document Type and Number:

Japanese Patent JP3888808

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To perform surely verifying operation at the erasing/verifying time in an NAND type non-volatile memory whose threshold voltage is negative in an erasing state.
SOLUTION: This memory has a constant current source 7 connected to a bit line to which a memory cell MC is connected, a sense amplifier section having a detecting transistor N8 detecting a potential of the connection point, a first reference potential ARVss being opposite side of a bit line of a memory cell, and a second reference potential PBVss to which a source of the N8 is connected. At the erasion/verifying time, ARVss and PBVss are controlled at the prescribed positive potential. The control gate level of a memory cell can be made into a negative level being equivalently a erasion/verifying level by controlling ARVss at a positive potential, further, equivalent threshold voltage of the N8 can be higher, or an equivalent trip level of a detecting inverter can be higher by controlling PBVss at a positive potential, and a detecting transistor can be made surely non-conduction at the time of erasion/verifying.

Inventors:

Kawamura Shoichi

Application Number:

JP23007399A

Publication Date:

March 07, 2007

Filing Date:

August 16, 1999

Export Citation:

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