Title:
NETWORK INTERFACING CIRCUIT
Document Type and Number:
Japanese Patent JP3908928
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a network interface circuit by ASIC, in which the rise in cost is prevented by managing frame data and simplifying the circuit constitution.
SOLUTION: In the network interface circuit loaded to an imaging apparatus, in which the network interface is integrated and ASIC designed to use a plurality of application functions with a system memory 9 as a shared resource, the ASIC is provided with MAC 1 for carrying out protocol control of a network 16, reception buffers 3 to 5 temporarily storing the frame data and a DMA controller part 6 controlling the reception buffers 3 to 5. In this case, the frame data stored to the reception buffers 3 to 5 are written into the system memory 9 via a DMA controller 6.
Inventors:
Toshio Takahashi
Application Number:
JP2001290164A
Publication Date:
April 25, 2007
Filing Date:
September 21, 2001
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F13/28; G06F13/38; H04N1/00; H04N1/21; (IPC1-7): G06F13/38; G06F13/28; H04N1/00; H04N1/21
Domestic Patent References:
| JP2000259523A | ||||
| JP2000259524A | ||||
| JP1175648A | ||||
| JP2001086122A | ||||
| JP2000200175A | ||||
| JP9062564A | ||||
| JP7064901A |
Attorney, Agent or Firm:
Hiroaki Sakai