Title:
ニューラル・ネットワーク処理要素
Document Type and Number:
Japanese Patent JP7490572
Kind Code:
B2
Abstract:
Described is a neural network accelerator tile. It includes an activation memory interface for interfacing with an activation memory to receive a set of activation representations and a weight memory interface for interfacing with a weight memory to receive a set of weight representations, and a processing element. The processing element is configured to implement a one-hot encoder, a histogrammer, an aligner, a reducer, and an accumulation sub-element which process the set of activation representations and the set of weight representations to produce a set of output representations.
Inventors:
Moshobos, Andreas
Sharifi Mohadam, Seiye
Marmoud, Mostafa
Sharifi Mohadam, Seiye
Marmoud, Mostafa
Application Number:
JP2020562166A
Publication Date:
May 27, 2024
Filing Date:
April 25, 2019
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06N3/063; G06F17/10
Domestic Patent References:
| JP2016522495A |
Foreign References:
| WO2017201627A1 | ||||
| US9836691 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Osamu Miyazaki
Tadahiko Ito
Osamu Miyazaki
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