Title:
半導体記憶素子を用いたニューラルネットワーク演算回路
Document Type and Number:
Japanese Patent JP6914342
Kind Code:
B2
Abstract:
A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.
Inventors:
Masayoshi Nakayama
Kazuyuki Kono
Yuriko Hayata
Takashi Ono
Reiji Mochida
Kazuyuki Kono
Yuriko Hayata
Takashi Ono
Reiji Mochida
Application Number:
JP2019540869A
Publication Date:
August 04, 2021
Filing Date:
August 21, 2018
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G06N3/063; G06G7/60
Domestic Patent References:
| JP6028331A | ||||
| JP4054685A | ||||
| JP5282269A |
Foreign References:
| US5371834 |
Attorney, Agent or Firm:
Hiromori Arai
Eisaku Teratani
Shinichi Michisaka
Eisaku Teratani
Shinichi Michisaka