Title:
不揮発性半導体記憶素子を用いたニューラルネットワーク演算回路
Document Type and Number:
Japanese Patent JP6956191
Kind Code:
B2
Abstract:
A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.
Inventors:
Reiji Mochida
Kazuyuki Kono
Yuriko Hayata
Takashi Ono
Masayoshi Nakayama
Kazuyuki Kono
Yuriko Hayata
Takashi Ono
Masayoshi Nakayama
Application Number:
JP2019540951A
Publication Date:
November 02, 2021
Filing Date:
September 03, 2018
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G06N3/063; G06G7/60; G11C11/54
Domestic Patent References:
| JP5264645A | ||||
| JP6131487A | ||||
| JP6028331A |
Foreign References:
| US5256911 | ||||
| US5155802 | ||||
| US20080172385 |
Attorney, Agent or Firm:
Hiromori Arai
Eisaku Teratani
Shinichi Michisaka
Eisaku Teratani
Shinichi Michisaka