Title:
３ゲート不揮発性メモリセルのアレイを使用するニューラルネットワーク分類子
Document Type and Number:
Japanese Patent JP7391097
Kind Code:
B2
Abstract:
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
Inventors:
Trang, Hugh, Van
Remke, Stephen
Tiwari, bipin
Doe, Nan
Latency, mark
Remke, Stephen
Tiwari, bipin
Doe, Nan
Latency, mark
Application Number:
JP2021541294A
Publication Date:
December 04, 2023
Filing Date:
August 29, 2019
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G06N3/063; G06G7/60; G11C11/54; G11C16/04; H01L21/336; H01L29/788; H01L29/792
Domestic Patent References:
| JP3174679A | ||||
| JP5335506A |
Foreign References:
| US6023422 | ||||
| US20170337466 |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office