Title:
ニューロモーフィック記憶回路、それを動作させるための方法、およびそのコンピュータ・プログラム
Document Type and Number:
Japanese Patent JP6591548
Kind Code:
B2
Abstract:
A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
Inventors:
Kim, sambom
Ram, Chong, Hong
Ram, Chong, Hong
Application Number:
JP2017533259A
Publication Date:
October 16, 2019
Filing Date:
January 05, 2016
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G11C11/54; G06G7/60; G06N3/063
Foreign References:
| US20120084241 | ||||
| WO2010133399A1 |
Other References:
Z.WANG et al.,A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems,FRONTIERS IN NEUROSCIENCE,スイス,FRONTIERS MEDIA SA,2015年 1月15日,Volume 8, Article 438,pp.1-11,doi: 10.3389/fnins.2014.00438
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Tasaichi Tanae