Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NOISE LEVEL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5834369
Kind Code:
A
Abstract:

PURPOSE: To obtain an output which corresponds to a noise level stably even when a power source is turned on, by supplying a voltage to a charging and discharging circuit only for a specified time from the powering-up time without the intervention of a circuit with an extremely large charging time constant.

CONSTITUTION: A signal input is supplied to a rectifying circuit 3 which rectifies and charges the signal abruptly and discharges it abruptly, and when the potential of its rectification output is higher than the emitter potential of a transistor (TR)8, the TR 8 turns off. Consequently, a capacitor 9 is charged with the rectification output through a resistor 7 having an extremely large resistance value and only a stationary noise output which varies slowly appears at a terminal 15. When a power source is turned on, on the other hand, a TR 11 is still in off state until the potential of a capacitor 14 attains to a prescribed value, so the capacitor 9 is charged with a power source voltage a diode 10. When the output potential of the rectifying circuit 3 is lower than the output potential of a presetting circuit 2, the TR 8 turns on and the potential of the capacitor 9 becomes equal to the rectification output potential.


Inventors:
ISHIZAKA TETSUO
Application Number:
JP13353781A
Publication Date:
February 28, 1983
Filing Date:
August 26, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
G01R19/02; G01R19/00; (IPC1-7): G01R19/02
Attorney, Agent or Firm:
Uchihara Shin



 
Previous Patent: ダンパ制御装置

Next Patent: MULTIPLE WAVE ANALYZER