Title:
ノイズ低減装置
Document Type and Number:
Japanese Patent JP3523243
Kind Code:
B1
Abstract:
A noise reduction circuit suppressing noise ascribable to a bit error to prevent the data quality from being lowered includes a data storage storing input data chronologically continuously supplied. The data storage includes three data registers connected in tandem to each other. The noise detector detects the magnitude of the noise, using three pieces of data respectively supplied from the three data registers to feed an output selector with an output selection signal, selecting noise correction or non-correction, depending on the comparison of the magnitude of the detected noise with a preset threshold. The output selector outputs either one of the inherent input data to be output and correction data calculated by a correction value calculator, depending on the output selection signal, to perform correction on the noise larger than the threshold value.
Inventors:
下迫田 義則
Application Number:
JP2002288182A
Publication Date:
April 26, 2004
Filing Date:
October 01, 2002
Export Citation:
Assignee:
沖電気工業株式会社
International Classes:
H04L1/00; G10L19/00; H04B1/10; (IPC1-7): H04L1/00; H04B1/10
Attorney, Agent or Firm:
香取 孝雄