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Title:
NON-VOLATILE MEMORY READING METHOD
Document Type and Number:
Japanese Patent JP2008226422
Kind Code:
A
Abstract:

To provide a non-volatile memory reading method for preventing a read disturbance phenomenon.

The method comprises: a step for discharging bit lines to a low voltage level, a step for applying a reading voltage or pass voltage to word lines connected to memory cells, a step for pre-charging the bit line connected to a specific memory cell to be read to a high voltage, and a step for evaluating the voltage level of the bit line and detecting data stored in the specific cell depending on the voltage level of the evaluated bit line. Therefore, a hot carrier injection phenomenon can be prevented from occurring around the memory cell to be read so that threshold voltages of the surrounding memory cells is changed and read disturbance is prevented.


Inventors:
PARK SEISAI
Application Number:
JP2007213285A
Publication Date:
September 25, 2008
Filing Date:
August 20, 2007
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
G11C16/04; G11C16/02; G11C16/06
Domestic Patent References:
JP2002358792A2002-12-13
JP2005276407A2005-10-06
JPH11273369A1999-10-08
Attorney, Agent or Firm:
Hiroyuki Nakagawa