To provide a non-volatile semiconductor memory device and a memory management method for facilitating countermeasures to any status abnormality in a much few of status information areas.
The non-volatile semiconductor memory device includes a memory control unit for controlling end batch erasure processing by memory cell block units, write-in processing by storage area units or bit units having the predetermined number of addresses, and data update processing of transferring predetermined data from a data update source memory cell block to a data update destination memory cell block by memory cell block units to a non-volatile memory. Each of the plurality of memory cell blocks includes: a status information storage area for storing status information including information about the usage state of the memory cell block; and an update history information storage area for storing update history information including an update history in the data update processing of the memory cell block. The memory cell block which is being used at present is specified on the basis of the status information and the update history information.
WO/2009/155123 | MEMORY MALFUNCTION PREDICTION SYSTEM AND METHOD |
JP5981906 | Image forming device |
JP2013080450 | MEMORY DEVICE |
SATO JIRO
JP2003150441A | 2003-05-23 | |||
JPH04344993A | 1992-12-01 | |||
JP2001101087A | 2001-04-13 | |||
JP2003150441A | 2003-05-23 | |||
JPH04344993A | 1992-12-01 |
Masanori Sugawara
Next Patent: PERIODIC TIMER WITH AUTOMATIC CORRECTING FUNCTION