Title:
ビットラインの高電圧が漏洩されることを防止する不揮発性半導体メモリ装置
Document Type and Number:
Japanese Patent JP4737975
Kind Code:
B2
Abstract:
The device has bitlines arranged adjacent to each other. A high voltage switching circuit (200) is structured to operate in a voltage. Another circuit (250) isolates the former circuit from the bitlines when another voltage greater than the former voltage is applied to the bitlines. A third circuit (300) is structured to isolate the circuit (200) from the latter circuit when the latter voltage is applied to the bitlines. An independent claim is also included for a method of preventing bitline high voltage from discharge using a nonvolatile semiconductor memory device.
Inventors:
Zhao Satoshi
Lee
Lee
Application Number:
JP2004344984A
Publication Date:
August 03, 2011
Filing Date:
November 29, 2004
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C16/06; G11C5/06; G11C16/04; G11C16/14; G11C16/24; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2001167590A | ||||
| JP2000021186A | ||||
| JP2002251896A | ||||
| JP10188580A | ||||
| JP10223866A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro