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Title:
NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS TEST METHOD
Document Type and Number:
Japanese Patent JP2002367399
Kind Code:
A
Abstract:

To provide a non-volatile semiconductor memory in which tests of peripheral circuits of a memory and wiring can be performed without performing write-in for a memory cell.

In the non-volatile semiconductor memory, control gates of a memory cell arranged in the same row in a memory cell array are connected in common first word lines connected to a row decoder and drains of a memory cell arranged in the same column in the memory cell array are connected in common, and first bit lines connected to a column selection gate is included, the non-volatile semiconductor memory is provided with a first switch arranged between the memory cell array and a first ROM and a second switch arranged between the memory cell array and a second ROM, and in testing, the first and the second switches are controlled so that data can be read out from the first ROM and the second ROM.


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Inventors:
MORI TOSHIKI
Application Number:
JP2001174587A
Publication Date:
December 20, 2002
Filing Date:
June 08, 2001
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11C16/02; G11C17/00; G11C29/00; G11C29/12; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G11C16/02; G11C17/00
Attorney, Agent or Firm:
Ikeuchi, Sato & Partners



 
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