Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3740212
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable one non-volatile memory cell to store quarternary information.
SOLUTION: Writing operation is performed by applying different three kinds of voltage to a word line successively at the time of verifying operation, and threshold voltage of a memory cell is controlled. At the time, writing data of binary (1 bit) corresponding to information of quarternary (2 bits) to be written are synthesized by a writing data conversion circuit (1) every three writing operations, information of quarternary (2 bits) is written in one memory cell, thereby doubling storage capacity of a flash memory. In reading out information, different three kinds of voltage is applied to a word line, read out three kinds of information of binary (1 bit) are synthesized by a read-out conversion circuit (2), and storage information of a memory cell is converted to information of two bits.
Inventors:
Yuno Shirono
Takayuki Kawahara
Katsutaka Kimura
Takayuki Kawahara
Katsutaka Kimura
Application Number:
JP11074896A
Publication Date:
February 01, 2006
Filing Date:
May 01, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/02; G11C17/00; G11C11/56; (IPC1-7): G11C16/04; G11C16/06
Domestic Patent References:
| JP4057294A | ||||
| JP7169284A | ||||
| JP6060674A | ||||
| JP1159895A | ||||
| JP7093979A |
Attorney, Agent or Firm:
Shizuyo Tamamura