PURPOSE: To obtain a non-volatile semiconductor memory capable of performing a test in which reliability for defective erasing or defective writing is high.

CONSTITUTION: When a function of a status register 18 is tested, a test mode signal is outputted from a test mode circuit 8, and an erasing pulse counter 7 is operated. The erasing pulse counter 7 counts an erasing pulse outputted from a program/erasing voltage generating circuit 5 only one time, a counted value is outputted to the program/erasing voltage generating circuit 5. The program/erasing voltage generating circuit 5 outputs an erasing pulse to a memory cell in a memory cell array 15 only one time in accordance with a counted value of the erasing pulse counter 7, and a state of erasing error is caused. The status register 18 is tested by reading out data of the status register 18 in this state, a test for an erasing error is performed using the status register 18 operating normally.