To allow gain variation in a nonlinear arithmetic circuit by a MOS circuit; to reduce variation of a gain characteristic by a process or temperature dependence; and to allow application of various kinds of nonlinear operations.

This nonlinear arithmetic circuit 1 has two multipliers 10, 20 and an operational amplifier 30. An output terminal of one multiplier of the two multipliers is connected to a positive phase input terminal of the operational amplifier 30, and an output terminal of the other multiplier of the two multipliers is connected to a reverse phase input terminal. One input terminal of one multiplier of the two multipliers is connected to an output terminal of the operational amplifier 30. Thereby, operational output of the operational amplifier is fed back to the multiplier.