Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND CONTROL METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2009088446
Kind Code:
A
Abstract:

To provide a nonvolatile semiconductor memory device capable easily specifying a region in which a failure has occurred in stacking semiconductor devices, and improving a data writing reliability, and to provide a control method of the nonvolatile semiconductor memory device.

A plurality of electrically rewritable memory elements formed at cross points of a semiconductor layer and a conductive layer, include a plurality of conductor layers alternately laminated on a substrate and a plurality of insulating layers. In the laminated layers, at least of one layer of a plurality of conductive layers or a plurality of insulating layers is different from other conductive layers or insulating layers in physical properties. A semiconductor layer is formed on a surface of a conductive layer and an insulating layer exposed by a plurality of memory plug holes extending from an upper face of the laminated layers to the substrate layer. Each of a plurality of memory elements includes a control electrode, and each of the control electrodes includes a memory string having a plurality of memory elements connected to a plurality of conductive layers.


Inventors:
MIZUKAMI MAKOTO
ARAI FUMITAKA
Application Number:
JP2007259827A
Publication Date:
April 23, 2009
Filing Date:
October 03, 2007
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L21/8246; H01L27/105; H01L27/112; H01L29/788; H01L29/792
Domestic Patent References:
JP2000222895A2000-08-11
JP2007180389A2007-07-12
JP2003078044A2003-03-14
JPH11135742A1999-05-21
JP2001185695A2001-07-06
JP2000222895A2000-08-11
JPH09306910A1997-11-28
Attorney, Agent or Firm:
Takahashi Hayashi & Partners