Title:
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD
Document Type and Number:
Japanese Patent JP2022121105
Kind Code:
A
Abstract:
To provide a nonvolatile semiconductor storage device capable of reducing latency due to correction processing of a read voltage.SOLUTION: In a memory 3, dummy data DD having a first data region R1 having more "0" than "1" of binary logic and a second data region R2 having more "1" than "0" of binary logic is stored. An ECC processing unit 11 detects a first error bit number V1 relating to the first data region R1 and a second error bit number V2 relating to the second data region R2. A calculation unit 12 calculates a relative difference X between the first error bit number V1 and the second error bit number V2. A comparison unit 13 compares the relative difference X with a predetermined value K1. A correction unit 14 corrects a read voltage Vr based on the result of the comparison by the comparison unit 13.SELECTED DRAWING: Figure 1
Inventors:
NAKAI SHUNSUKE
KAWAMURA ATSUSHI
MARUKE YASUHISA
CHIN KANTATSU
KAWAMURA ATSUSHI
MARUKE YASUHISA
CHIN KANTATSU
Application Number:
JP2021018273A
Publication Date:
August 19, 2022
Filing Date:
February 08, 2021
Export Citation:
Assignee:
MEGA CHIPS CORP
International Classes:
G11C16/34; G06F11/10; G06F12/00; G11C11/56; G11C16/04; G11C16/08
Attorney, Agent or Firm:
Masataka Kotani
Etsushi Kotani
Kengo Takao
Etsushi Kotani
Kengo Takao
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