Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3344331
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable further high-speed read-out.
SOLUTION: This flash memory comprises a memory cell array 17, a row address buffer 18, a row decoder 19, row driver 20, a column address buffer 21, a column decoder 22, a column selector 23, a sense amplifier circuit 24, a write circuit 25 and a control circuit 26. Memory cells MC11,..., MCnk are selected when data is read not by a control gate of a memory transistor, but by controlling a switching transistor with normal voltage.
Inventors:
Masahiko Kashimura
Application Number:
JP29467698A
Publication Date:
November 11, 2002
Filing Date:
September 30, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C11/41; G11C16/02; G11C16/04; G11C16/26; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C11/41; G11C16/04; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP7297304A | ||||
| JP3159273A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)