PURPOSE: To reduce the area of a memory cell, by forming a high impurity concentration region including a tunnel insulating film region in a planar shape having a parallel facing sides, dividing a part, where a floating gate is overlapped on the high impurity concentration region, and providing the overlapped parts at positions along the parallel sides of the high impurity concentration region so as to face said sides.

CONSTITUTION: Regions 1a and 1b of a floating gate 1, which is formed on a tunnel oxide film 6, are provided at positions facing a pair of facing sides of a high impurity concentration region 5 in the direction Y. The parts 1a and 1b, where the high impurity concentration region 5 is overlapped with the floating gate 1, are the regions, where a tunnel current flows. The regions 1a and 1b, where the tunnel current flows, are provided along the pair of parallel sides of the high impurity concentration region 5 so as to face said sides. Therefore, the sum of the areas of the regions 1a and 1b is not changed even if a mask is deviated in a photoengraving step and the relative positional relation between the regions 1a and 1b, and the high impurity concentration region 5 is changed. Thus the writing and erasing characteristics of an EEPROM are not changed.