NONVOLATILE SEMICONDUCTOR MEMORY HAVING NAND CELL STRUCTURE

Japanese Patent JP3778368

B2

PURPOSE: To obtain a memory cell structure which can prevent current consumption from increasing at a standby time caused by dielectric breakdown of a memory cell and also make it hard for a bridge phenomenon to occur by relieving a bit line pitch in nonvolatile semiconductor memory in a NAND cell structure. CONSTITUTION: On a side of a bit line BL of a unit memory string consisting of memory cells (M10 to M1nD) which are serially connected, two string selection transistors (MS10D and MS11D) and on a side of the ground, two string selection/ground selection transistors (MG10D and MG11D) are provided and controlled by string selection signals (SS0 and S81) and ground selection signals (GS0 and GS1) respectively. The signals SS0 and SS1 are logic \'low\' at a standby time, and either of them becomes logic \'high\' when they are selected. Thus, because four transistors MS10D, MS11D, MG10D and MG11D are provided, four unit memory strings can be connected to the bit line BL and relieves a bit line pitch.