Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NORMALIZATION CIRCUIT
Document Type and Number:
Japanese Patent JPH10143593
Kind Code:
A
Abstract:

To accelerate a normalization operation by multiplying the output signals of an offset means for supplying a DC offset to the output of a first multiplication means and the output of a delay means for supplying delay time equal to the delay time received by first input signals to second input signals.

The sum output R0 signals of a main beam are clamped for an APC period when a laser diode is OFF by a clamp amplifier 1 and a sample- and-hold circuit 2, an offset voltage 6 is supplied to the output V2 of a first multiplier 4 in a DC shifter 5 further and it is supplied to a second multiplier 7. In the meantime, the difference output CMO signals of a side beam are offset and clamped for the APC period by the clamp amplifier 8, the sample-and-hold circuit 9 and a clamp reference 10. Delay equal to the operation delay time of the first multiplier 4 is supplied to the clamped value in a delay circuit 11 and it is supplied to the second multiplier 7. Then, the relative time difference of two input Vx and Yy in the second multiplier 7 is turned to 0.


Inventors:
KANEKO SHINJI
OOURA SEIJI
Application Number:
JP30312196A
Publication Date:
May 29, 1998
Filing Date:
November 14, 1996
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SONY CORP
International Classes:
G06G7/16; G11B7/00; G11B7/005; (IPC1-7): G06G7/16; G11B7/00