Title:
Offset cancellation for a continuous time circuit
Document Type and Number:
Japanese Patent JP6106358
Kind Code:
B2
Abstract:
One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.
Inventors:
Sriam Narayan
Xiao Yang Sue
Sir Jay Shmaleyev
Xiao Yang Sue
Sir Jay Shmaleyev
Application Number:
JP2011255026A
Publication Date:
March 29, 2017
Filing Date:
November 22, 2011
Export Citation:
Assignee:
Altera Corporation
International Classes:
H03F3/34
Domestic Patent References:
| JP2009089311A | ||||
| JP8223228A | ||||
| JP2003283266A |
Foreign References:
| US6914479 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita
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