Title:
ワンタイムプログラマブルメモリセル
Document Type and Number:
Japanese Patent JP2005518063
Kind Code:
A
Abstract:
The invention relates to a memory cell with a binary value consisting of two parallel branches. Each of said branches comprises: at least one polycrystalline silicon programming resistor (Rp 1 , Rp 2 ), which is connected between a first supply terminal ( 1 ) and a point or terminal for the differential reading ( 4, 6 ) of the memory cell state; and at least one first switch (MNP 1 , MNP 2 ) which, during programming, connects one of said read terminals to a second supply terminal ( 2 ).
Inventors:
Barduyer Michel
Resor Pierre
Marelbe Alexandre
Vidal Luk
Resor Pierre
Marelbe Alexandre
Vidal Luk
Application Number:
JP2003568666A
Publication Date:
June 16, 2005
Filing Date:
February 11, 2003
Export Citation:
Assignee:
STMicroelectronics Society Anonymous
International Classes:
G06F21/75; G06F21/86; G11C17/14; H01L27/10; G11C16/22; (IPC1-7): G11C17/14; G06F12/14; H01L27/10
Attorney, Agent or Firm:
Keiichi Yamamoto