Title:
演算増幅器
Document Type and Number:
Japanese Patent JP4789136
Kind Code:
B2
Abstract:
A differential amplifier includes an input stage circuit including a first differential pair and a second differential pair which are complementary to each other; a first current mirror circuit connected with the first differential pair and configured to function as an active load; a second current mirror circuit connected with the second differential pair and configured to function as an active load; an output stage circuit having a pair of output transistors connected in series between a higher power supply and a lower power supply; an operation point setting circuit configured to set an operation point of the output transistors; and a floating constant current source connected between an input terminal of the first current mirror circuit and an input terminal of the second current mirror circuit, and configured to supply a constant current. The first current mirror circuit and the second current mirror circuit supply superimpose an output of the input stage circuit on a current corresponding to the constant current by the floating constant current source to supply to the operation point setting circuit.
Inventors:
Koichi Nishimura
Atsushi Shimatani
Motoyasu Ichimura
Atsushi Shimatani
Motoyasu Ichimura
Application Number:
JP2005110646A
Publication Date:
October 12, 2011
Filing Date:
April 07, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03F3/45; H03F3/16; H03F3/34
Domestic Patent References:
| JP11150427A | ||||
| JP7058872B2 | ||||
| JP2004201064A | ||||
| JP1202003A | ||||
| JP6326529A | ||||
| JP2005057744A |
Foreign References:
| US20050068105 |
Attorney, Agent or Firm:
Minoru Kudo