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Title:
OPERATION SWITCHING CIRCUIT
Document Type and Number:
Japanese Patent JPS6175616
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption by designing the circuit that all transistors (TRs) constituting the 1wt and 2nd AD converters are not operated at the same time, a current flowing to them is reduced by resistors and the output current is interrupted in response to the level of a control signal.

CONSTITUTION: The TRs Q1, Q2 constitute the 1st A/D converter and the TRs Q3, Q4 constitute the 2nd A/D converter. Then a voltage level of the control signal VC is changed into three stages; L, M, H. Suppose that the control signal VC is at an L level, the TRs Q1, Q4 are turned off and a current path comprising the TRs Q5, Q2, a resistor R1 and the TRQ3 is formed. Since the resistor R1 is provided, the amount of the current flowing the said current path is reduced. Then the level of the collector voltage V0 of the TRQ2 is dropped and an output voltage VA goes to a high level by the voltage drop of an output current I0 and a resistor R6.


Inventors:
YAMAMOTO MOROHISA
FURUHATA MAKOTO
ARAI IZUMI
Application Number:
JP19670284A
Publication Date:
April 18, 1986
Filing Date:
September 21, 1984
Export Citation:
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Assignee:
HITACHI MICROCUMPUTER ENG
HITACHI LTD
International Classes:
H03K17/00; H03M1/36; (IPC1-7): H03K17/00
Domestic Patent References:
JPS5121498A1976-02-20
JPS4816563A
JPS4917898A1974-02-16
JPS53142856A1978-12-12
JPS5449844U1979-04-06
Attorney, Agent or Firm:
Tomio Dainichi



 
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