Title:
OPERATION VERIFYING METHOD FOR MEMORY TEST PATTERN, SEMICONDUCTOR TEST DEVICE, AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002109898
Kind Code:
A
Abstract:
To shorten the time of the operation verification of a memory test pattern and to eliminate misverification.
Address information needed to analyze the memory test pattern operation is read out of a memory test pattern source 2 to calculates address operation and a pattern operation analytic log 5 for the pattern operation analysis is generated; and address operation in command performance is extracted from the pattern operation analytic log 5 to generate a pattern operation grasping log 7. Further, the generation order and intervals between commands are extracted from the pattern operation analytic log 5 to generate a command performance interval grasping log 9.
Inventors:
NAKANO TOSHIO
Application Number:
JP2000301647A
Publication Date:
April 12, 2002
Filing Date:
October 02, 2000
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R31/28; G06F11/22; G06F12/16; G11C29/00; G11C29/10; G11C29/12; G01R31/3183; (IPC1-7): G11C29/00; G01R31/3183; G01R31/28; G06F11/22; G06F12/16
Attorney, Agent or Firm:
Keigo Murakami (3 outside)